;;*****************************************************************************
;;*****************************************************************************
;;  FILENAME:   TRIADC_1.inc
;;  Version: 2.2, Updated on 2004/08/05 at 10:19:32
;;  Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
;;
;;  DESCRIPTION:  Assembler declarations for the TriADC User Module for the
;;                27xxx PSoC family of devices.
;;
;;-----------------------------------------------------------------------------
;;  Copyright (c) Cypress MicroSystems 2000-2003. All Rights Reserved.
;;*****************************************************************************
;;*****************************************************************************


;--------------------------------------------------
; Contants for TRIADC_1 API's.
;--------------------------------------------------
; Counter1 Constants
TRIADC_1_bfCounter1_Mask:              equ   02h
TRIADC_1_bfCounter1_INT_REG:           equ   0e1h

; Counter2 Constants
TRIADC_1_bfCounter2_Mask:              equ   04h
TRIADC_1_bfCounter2_INT_REG:           equ   0dfh

; Counter3 Constants
TRIADC_1_bfCounter3_Mask:              equ   08h
TRIADC_1_bfCounter3_INT_REG:           equ   0dfh

; PWM Constants
TRIADC_1_bfPWM16_Mask:                 equ   80h
TRIADC_1_bfPWM16_INT_REG:              equ   0e1h

; Power Settings
TRIADC_1_bfPOWERMASK:                  equ   03h
TRIADC_1_OFF:                          equ   00h
TRIADC_1_LOWPOWER:                     equ   01h
TRIADC_1_MEDPOWER:                     equ   02h
TRIADC_1_HIGHPOWER:                    equ   03h

; Parameter Settings
TRIADC_1_bNUMBITS:                     equ   ch
TRIADC_1_bCALCTIME:                    equ   7fffh
TRIADC_1_bMAXRES:                      equ   0Dh      ; Max resolution 13 bits
TRIADC_1_bMINRES:                      equ   07h      ; Min resolution 7 bits
TRIADC_1_fCOMPARE_TRUE:                equ   08h      ; Bit to enable compare True interrupts

; Functionality constants
TRIADC_1_fFSW0:                        equ   10h      ; Switch Cap FSW0 switch enable
TRIADC_1_NoAZ:                         equ   01h      ; Set if AutoZero is no enabled
TRIADC_1_fAutoZero:                    equ   20h      ; Switch Cap AutoZero switch enable
TRIADC_1_fDBLK_ENABLE:                 equ   01h      ; Digital block enable bit
TRIADC_1_fPULSE_WIDE:                  equ   04h      ; Set to wide terminal count pulse

; fStatus definitions
TRIADC_1_fDATA_READY:                  equ   10h      ; This bit is set when data is available
TRIADC_1_bRES_MASK:                    equ   0Fh      ; This bit while in integrate cycle

; Data Format
TRIADC_1_DATA_FORMAT:                  equ   0

; Flag in CR2 register mask
TRIADC_1_fRES_SET:                     equ   01h

;--------------------------------------------------
; Register Address Contstants for TRIADC_1
;--------------------------------------------------
; Integrator1 Block Register Definitions
TRIADC_1_bfADC1cr0: equ 80h
TRIADC_1_bfADC1cr1: equ 81h
TRIADC_1_bfADC1cr2: equ 82h
TRIADC_1_bfADC1cr3: equ 83h
; Integrator2 Block Register Definitions
TRIADC_1_bfADC2cr0: equ 94h
TRIADC_1_bfADC2cr1: equ 95h
TRIADC_1_bfADC2cr2: equ 96h
TRIADC_1_bfADC2cr3: equ 97h
; Integrator3 Block Register Definitions
TRIADC_1_bfADC3cr0: equ 8ch
TRIADC_1_bfADC3cr1: equ 8dh
TRIADC_1_bfADC3cr2: equ 8eh
TRIADC_1_bfADC3cr3: equ 8fh

; Counter1 Block Register Definitions
TRIADC_1_fCounter1FN:   equ 24h
TRIADC_1_fCounter1SL:   equ 25h
TRIADC_1_fCounter1OS:   equ 26h
TRIADC_1_bCount1:   equ 24h
TRIADC_1_bPeriod1:  equ 25h
TRIADC_1_bCompare1: equ 26h
TRIADC_1_bCounter1_CR0: equ 27h

; Counter2 Block Register Definitions
TRIADC_1_fCounter2FN:   equ 48h
TRIADC_1_fCounter2SL:   equ 49h
TRIADC_1_fCounter2OS:   equ 4ah
TRIADC_1_bCount2:   equ 48h
TRIADC_1_bPeriod2:  equ 49h
TRIADC_1_bCompare2: equ 4ah
TRIADC_1_bCounter2_CR0: equ 4bh


; Counter3 Block Register Definitions
TRIADC_1_fCounter3FN:   equ 4ch
TRIADC_1_fCounter3SL:   equ 4dh
TRIADC_1_fCounter3OS:   equ 4eh
TRIADC_1_bCount3:   equ 4ch
TRIADC_1_bPeriod3:  equ 4dh
TRIADC_1_bCompare3: equ 4eh
TRIADC_1_bCounter3_CR0: equ 4fh

; PWM16 Block Register Definitions
TRIADC_1_bfPWM_LSB_FN:  equ 38h
TRIADC_1_bfPWM_MSB_FN:  equ 3ch
TRIADC_1_fPWM_LSB_CR0:  equ 3bh
TRIADC_1_fPWM_MSB_CR0:  equ 3fh
TRIADC_1_bPWM_Count_MSB:    equ 3ch
TRIADC_1_bPWM_Count_LSB:    equ 38h
TRIADC_1_bPWM_Period_MSB:   equ 3dh
TRIADC_1_bPWM_Period_LSB:   equ 39h
TRIADC_1_bPWM_IntTime_MSB:  equ 3eh
TRIADC_1_bPWM_IntTime_LSB:  equ 3ah
TRIADC_1_bfPWM_LSB_FN:  equ 38h
TRIADC_1_bfPWM_MSB_FN:  equ 3ch

; end of file TRIADC_1.inc

