/******************************************************************************
*  Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
******************************************************************************/
/*
*   PSoCGPIOINT.h
*   Data: 04 June, 2002
*   Copyright Cypress MicroSystems 2002
*
*  This file is generated by the Device Editor on Application Generation.
*  It contains equates that are useful in writing code relating to GPIO
*  related values.
*  
*  DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
*  Edits to this file will not be preserved.
*/
#include <m8c.h>
// QP1B address and mask defines
#pragma	ioport	QP1B_Data_ADDR:	0x8
BYTE			QP1B_Data_ADDR;
#pragma	ioport	QP1B_DriveMode_0_ADDR:	0x108
BYTE			QP1B_DriveMode_0_ADDR;
#pragma	ioport	QP1B_DriveMode_1_ADDR:	0x109
BYTE			QP1B_DriveMode_1_ADDR;
#pragma	ioport	QP1B_DriveMode_2_ADDR:	0xb
BYTE			QP1B_DriveMode_2_ADDR;
#pragma	ioport	QP1B_GlobalSelect_ADDR:	0xa
BYTE			QP1B_GlobalSelect_ADDR;
#pragma	ioport	QP1B_IntCtrl_0_ADDR:	0x10a
BYTE			QP1B_IntCtrl_0_ADDR;
#pragma	ioport	QP1B_IntCtrl_1_ADDR:	0x10b
BYTE			QP1B_IntCtrl_1_ADDR;
#pragma	ioport	QP1B_IntEn_ADDR:	0x9
BYTE			QP1B_IntEn_ADDR;
#define QP1B_MASK 0x8
// QP0B address and mask defines
#pragma	ioport	QP0B_Data_ADDR:	0x8
BYTE			QP0B_Data_ADDR;
#pragma	ioport	QP0B_DriveMode_0_ADDR:	0x108
BYTE			QP0B_DriveMode_0_ADDR;
#pragma	ioport	QP0B_DriveMode_1_ADDR:	0x109
BYTE			QP0B_DriveMode_1_ADDR;
#pragma	ioport	QP0B_DriveMode_2_ADDR:	0xb
BYTE			QP0B_DriveMode_2_ADDR;
#pragma	ioport	QP0B_GlobalSelect_ADDR:	0xa
BYTE			QP0B_GlobalSelect_ADDR;
#pragma	ioport	QP0B_IntCtrl_0_ADDR:	0x10a
BYTE			QP0B_IntCtrl_0_ADDR;
#pragma	ioport	QP0B_IntCtrl_1_ADDR:	0x10b
BYTE			QP0B_IntCtrl_1_ADDR;
#pragma	ioport	QP0B_IntEn_ADDR:	0x9
BYTE			QP0B_IntEn_ADDR;
#define QP0B_MASK 0x2
// QP0A address and mask defines
#pragma	ioport	QP0A_Data_ADDR:	0x8
BYTE			QP0A_Data_ADDR;
#pragma	ioport	QP0A_DriveMode_0_ADDR:	0x108
BYTE			QP0A_DriveMode_0_ADDR;
#pragma	ioport	QP0A_DriveMode_1_ADDR:	0x109
BYTE			QP0A_DriveMode_1_ADDR;
#pragma	ioport	QP0A_DriveMode_2_ADDR:	0xb
BYTE			QP0A_DriveMode_2_ADDR;
#pragma	ioport	QP0A_GlobalSelect_ADDR:	0xa
BYTE			QP0A_GlobalSelect_ADDR;
#pragma	ioport	QP0A_IntCtrl_0_ADDR:	0x10a
BYTE			QP0A_IntCtrl_0_ADDR;
#pragma	ioport	QP0A_IntCtrl_1_ADDR:	0x10b
BYTE			QP0A_IntCtrl_1_ADDR;
#pragma	ioport	QP0A_IntEn_ADDR:	0x9
BYTE			QP0A_IntEn_ADDR;
#define QP0A_MASK 0x1
// QP1A address and mask defines
#pragma	ioport	QP1A_Data_ADDR:	0x8
BYTE			QP1A_Data_ADDR;
#pragma	ioport	QP1A_DriveMode_0_ADDR:	0x108
BYTE			QP1A_DriveMode_0_ADDR;
#pragma	ioport	QP1A_DriveMode_1_ADDR:	0x109
BYTE			QP1A_DriveMode_1_ADDR;
#pragma	ioport	QP1A_DriveMode_2_ADDR:	0xb
BYTE			QP1A_DriveMode_2_ADDR;
#pragma	ioport	QP1A_GlobalSelect_ADDR:	0xa
BYTE			QP1A_GlobalSelect_ADDR;
#pragma	ioport	QP1A_IntCtrl_0_ADDR:	0x10a
BYTE			QP1A_IntCtrl_0_ADDR;
#pragma	ioport	QP1A_IntCtrl_1_ADDR:	0x10b
BYTE			QP1A_IntCtrl_1_ADDR;
#pragma	ioport	QP1A_IntEn_ADDR:	0x9
BYTE			QP1A_IntEn_ADDR;
#define QP1A_MASK 0x4
// A0 address and mask defines
#pragma	ioport	A0_Data_ADDR:	0x0
BYTE			A0_Data_ADDR;
#pragma	ioport	A0_DriveMode_0_ADDR:	0x100
BYTE			A0_DriveMode_0_ADDR;
#pragma	ioport	A0_DriveMode_1_ADDR:	0x101
BYTE			A0_DriveMode_1_ADDR;
#pragma	ioport	A0_DriveMode_2_ADDR:	0x3
BYTE			A0_DriveMode_2_ADDR;
#pragma	ioport	A0_GlobalSelect_ADDR:	0x2
BYTE			A0_GlobalSelect_ADDR;
#pragma	ioport	A0_IntCtrl_0_ADDR:	0x102
BYTE			A0_IntCtrl_0_ADDR;
#pragma	ioport	A0_IntCtrl_1_ADDR:	0x103
BYTE			A0_IntCtrl_1_ADDR;
#pragma	ioport	A0_IntEn_ADDR:	0x1
BYTE			A0_IntEn_ADDR;
#define A0_MASK 0x1
// A1 address and mask defines
#pragma	ioport	A1_Data_ADDR:	0x0
BYTE			A1_Data_ADDR;
#pragma	ioport	A1_DriveMode_0_ADDR:	0x100
BYTE			A1_DriveMode_0_ADDR;
#pragma	ioport	A1_DriveMode_1_ADDR:	0x101
BYTE			A1_DriveMode_1_ADDR;
#pragma	ioport	A1_DriveMode_2_ADDR:	0x3
BYTE			A1_DriveMode_2_ADDR;
#pragma	ioport	A1_GlobalSelect_ADDR:	0x2
BYTE			A1_GlobalSelect_ADDR;
#pragma	ioport	A1_IntCtrl_0_ADDR:	0x102
BYTE			A1_IntCtrl_0_ADDR;
#pragma	ioport	A1_IntCtrl_1_ADDR:	0x103
BYTE			A1_IntCtrl_1_ADDR;
#pragma	ioport	A1_IntEn_ADDR:	0x1
BYTE			A1_IntEn_ADDR;
#define A1_MASK 0x2
// A2 address and mask defines
#pragma	ioport	A2_Data_ADDR:	0x0
BYTE			A2_Data_ADDR;
#pragma	ioport	A2_DriveMode_0_ADDR:	0x100
BYTE			A2_DriveMode_0_ADDR;
#pragma	ioport	A2_DriveMode_1_ADDR:	0x101
BYTE			A2_DriveMode_1_ADDR;
#pragma	ioport	A2_DriveMode_2_ADDR:	0x3
BYTE			A2_DriveMode_2_ADDR;
#pragma	ioport	A2_GlobalSelect_ADDR:	0x2
BYTE			A2_GlobalSelect_ADDR;
#pragma	ioport	A2_IntCtrl_0_ADDR:	0x102
BYTE			A2_IntCtrl_0_ADDR;
#pragma	ioport	A2_IntCtrl_1_ADDR:	0x103
BYTE			A2_IntCtrl_1_ADDR;
#pragma	ioport	A2_IntEn_ADDR:	0x1
BYTE			A2_IntEn_ADDR;
#define A2_MASK 0x4
// A3 address and mask defines
#pragma	ioport	A3_Data_ADDR:	0x0
BYTE			A3_Data_ADDR;
#pragma	ioport	A3_DriveMode_0_ADDR:	0x100
BYTE			A3_DriveMode_0_ADDR;
#pragma	ioport	A3_DriveMode_1_ADDR:	0x101
BYTE			A3_DriveMode_1_ADDR;
#pragma	ioport	A3_DriveMode_2_ADDR:	0x3
BYTE			A3_DriveMode_2_ADDR;
#pragma	ioport	A3_GlobalSelect_ADDR:	0x2
BYTE			A3_GlobalSelect_ADDR;
#pragma	ioport	A3_IntCtrl_0_ADDR:	0x102
BYTE			A3_IntCtrl_0_ADDR;
#pragma	ioport	A3_IntCtrl_1_ADDR:	0x103
BYTE			A3_IntCtrl_1_ADDR;
#pragma	ioport	A3_IntEn_ADDR:	0x1
BYTE			A3_IntEn_ADDR;
#define A3_MASK 0x8
// A4 address and mask defines
#pragma	ioport	A4_Data_ADDR:	0x0
BYTE			A4_Data_ADDR;
#pragma	ioport	A4_DriveMode_0_ADDR:	0x100
BYTE			A4_DriveMode_0_ADDR;
#pragma	ioport	A4_DriveMode_1_ADDR:	0x101
BYTE			A4_DriveMode_1_ADDR;
#pragma	ioport	A4_DriveMode_2_ADDR:	0x3
BYTE			A4_DriveMode_2_ADDR;
#pragma	ioport	A4_GlobalSelect_ADDR:	0x2
BYTE			A4_GlobalSelect_ADDR;
#pragma	ioport	A4_IntCtrl_0_ADDR:	0x102
BYTE			A4_IntCtrl_0_ADDR;
#pragma	ioport	A4_IntCtrl_1_ADDR:	0x103
BYTE			A4_IntCtrl_1_ADDR;
#pragma	ioport	A4_IntEn_ADDR:	0x1
BYTE			A4_IntEn_ADDR;
#define A4_MASK 0x10
// A5 address and mask defines
#pragma	ioport	A5_Data_ADDR:	0x0
BYTE			A5_Data_ADDR;
#pragma	ioport	A5_DriveMode_0_ADDR:	0x100
BYTE			A5_DriveMode_0_ADDR;
#pragma	ioport	A5_DriveMode_1_ADDR:	0x101
BYTE			A5_DriveMode_1_ADDR;
#pragma	ioport	A5_DriveMode_2_ADDR:	0x3
BYTE			A5_DriveMode_2_ADDR;
#pragma	ioport	A5_GlobalSelect_ADDR:	0x2
BYTE			A5_GlobalSelect_ADDR;
#pragma	ioport	A5_IntCtrl_0_ADDR:	0x102
BYTE			A5_IntCtrl_0_ADDR;
#pragma	ioport	A5_IntCtrl_1_ADDR:	0x103
BYTE			A5_IntCtrl_1_ADDR;
#pragma	ioport	A5_IntEn_ADDR:	0x1
BYTE			A5_IntEn_ADDR;
#define A5_MASK 0x20
// SLAVE_RX address and mask defines
#pragma	ioport	SLAVE_RX_Data_ADDR:	0x0
BYTE			SLAVE_RX_Data_ADDR;
#pragma	ioport	SLAVE_RX_DriveMode_0_ADDR:	0x100
BYTE			SLAVE_RX_DriveMode_0_ADDR;
#pragma	ioport	SLAVE_RX_DriveMode_1_ADDR:	0x101
BYTE			SLAVE_RX_DriveMode_1_ADDR;
#pragma	ioport	SLAVE_RX_DriveMode_2_ADDR:	0x3
BYTE			SLAVE_RX_DriveMode_2_ADDR;
#pragma	ioport	SLAVE_RX_GlobalSelect_ADDR:	0x2
BYTE			SLAVE_RX_GlobalSelect_ADDR;
#pragma	ioport	SLAVE_RX_IntCtrl_0_ADDR:	0x102
BYTE			SLAVE_RX_IntCtrl_0_ADDR;
#pragma	ioport	SLAVE_RX_IntCtrl_1_ADDR:	0x103
BYTE			SLAVE_RX_IntCtrl_1_ADDR;
#pragma	ioport	SLAVE_RX_IntEn_ADDR:	0x1
BYTE			SLAVE_RX_IntEn_ADDR;
#define SLAVE_RX_MASK 0x40
// SLAVE_TX address and mask defines
#pragma	ioport	SLAVE_TX_Data_ADDR:	0x0
BYTE			SLAVE_TX_Data_ADDR;
#pragma	ioport	SLAVE_TX_DriveMode_0_ADDR:	0x100
BYTE			SLAVE_TX_DriveMode_0_ADDR;
#pragma	ioport	SLAVE_TX_DriveMode_1_ADDR:	0x101
BYTE			SLAVE_TX_DriveMode_1_ADDR;
#pragma	ioport	SLAVE_TX_DriveMode_2_ADDR:	0x3
BYTE			SLAVE_TX_DriveMode_2_ADDR;
#pragma	ioport	SLAVE_TX_GlobalSelect_ADDR:	0x2
BYTE			SLAVE_TX_GlobalSelect_ADDR;
#pragma	ioport	SLAVE_TX_IntCtrl_0_ADDR:	0x102
BYTE			SLAVE_TX_IntCtrl_0_ADDR;
#pragma	ioport	SLAVE_TX_IntCtrl_1_ADDR:	0x103
BYTE			SLAVE_TX_IntCtrl_1_ADDR;
#pragma	ioport	SLAVE_TX_IntEn_ADDR:	0x1
BYTE			SLAVE_TX_IntEn_ADDR;
#define SLAVE_TX_MASK 0x80
// MOT0A address and mask defines
#pragma	ioport	MOT0A_Data_ADDR:	0x4
BYTE			MOT0A_Data_ADDR;
#pragma	ioport	MOT0A_DriveMode_0_ADDR:	0x104
BYTE			MOT0A_DriveMode_0_ADDR;
#pragma	ioport	MOT0A_DriveMode_1_ADDR:	0x105
BYTE			MOT0A_DriveMode_1_ADDR;
#pragma	ioport	MOT0A_DriveMode_2_ADDR:	0x7
BYTE			MOT0A_DriveMode_2_ADDR;
#pragma	ioport	MOT0A_GlobalSelect_ADDR:	0x6
BYTE			MOT0A_GlobalSelect_ADDR;
#pragma	ioport	MOT0A_IntCtrl_0_ADDR:	0x106
BYTE			MOT0A_IntCtrl_0_ADDR;
#pragma	ioport	MOT0A_IntCtrl_1_ADDR:	0x107
BYTE			MOT0A_IntCtrl_1_ADDR;
#pragma	ioport	MOT0A_IntEn_ADDR:	0x5
BYTE			MOT0A_IntEn_ADDR;
#define MOT0A_MASK 0x1
// MOT0B address and mask defines
#pragma	ioport	MOT0B_Data_ADDR:	0x4
BYTE			MOT0B_Data_ADDR;
#pragma	ioport	MOT0B_DriveMode_0_ADDR:	0x104
BYTE			MOT0B_DriveMode_0_ADDR;
#pragma	ioport	MOT0B_DriveMode_1_ADDR:	0x105
BYTE			MOT0B_DriveMode_1_ADDR;
#pragma	ioport	MOT0B_DriveMode_2_ADDR:	0x7
BYTE			MOT0B_DriveMode_2_ADDR;
#pragma	ioport	MOT0B_GlobalSelect_ADDR:	0x6
BYTE			MOT0B_GlobalSelect_ADDR;
#pragma	ioport	MOT0B_IntCtrl_0_ADDR:	0x106
BYTE			MOT0B_IntCtrl_0_ADDR;
#pragma	ioport	MOT0B_IntCtrl_1_ADDR:	0x107
BYTE			MOT0B_IntCtrl_1_ADDR;
#pragma	ioport	MOT0B_IntEn_ADDR:	0x5
BYTE			MOT0B_IntEn_ADDR;
#define MOT0B_MASK 0x2
// MOT1A address and mask defines
#pragma	ioport	MOT1A_Data_ADDR:	0x4
BYTE			MOT1A_Data_ADDR;
#pragma	ioport	MOT1A_DriveMode_0_ADDR:	0x104
BYTE			MOT1A_DriveMode_0_ADDR;
#pragma	ioport	MOT1A_DriveMode_1_ADDR:	0x105
BYTE			MOT1A_DriveMode_1_ADDR;
#pragma	ioport	MOT1A_DriveMode_2_ADDR:	0x7
BYTE			MOT1A_DriveMode_2_ADDR;
#pragma	ioport	MOT1A_GlobalSelect_ADDR:	0x6
BYTE			MOT1A_GlobalSelect_ADDR;
#pragma	ioport	MOT1A_IntCtrl_0_ADDR:	0x106
BYTE			MOT1A_IntCtrl_0_ADDR;
#pragma	ioport	MOT1A_IntCtrl_1_ADDR:	0x107
BYTE			MOT1A_IntCtrl_1_ADDR;
#pragma	ioport	MOT1A_IntEn_ADDR:	0x5
BYTE			MOT1A_IntEn_ADDR;
#define MOT1A_MASK 0x4
// MOT1B address and mask defines
#pragma	ioport	MOT1B_Data_ADDR:	0x4
BYTE			MOT1B_Data_ADDR;
#pragma	ioport	MOT1B_DriveMode_0_ADDR:	0x104
BYTE			MOT1B_DriveMode_0_ADDR;
#pragma	ioport	MOT1B_DriveMode_1_ADDR:	0x105
BYTE			MOT1B_DriveMode_1_ADDR;
#pragma	ioport	MOT1B_DriveMode_2_ADDR:	0x7
BYTE			MOT1B_DriveMode_2_ADDR;
#pragma	ioport	MOT1B_GlobalSelect_ADDR:	0x6
BYTE			MOT1B_GlobalSelect_ADDR;
#pragma	ioport	MOT1B_IntCtrl_0_ADDR:	0x106
BYTE			MOT1B_IntCtrl_0_ADDR;
#pragma	ioport	MOT1B_IntCtrl_1_ADDR:	0x107
BYTE			MOT1B_IntCtrl_1_ADDR;
#pragma	ioport	MOT1B_IntEn_ADDR:	0x5
BYTE			MOT1B_IntEn_ADDR;
#define MOT1B_MASK 0x8
// MOT2A address and mask defines
#pragma	ioport	MOT2A_Data_ADDR:	0x4
BYTE			MOT2A_Data_ADDR;
#pragma	ioport	MOT2A_DriveMode_0_ADDR:	0x104
BYTE			MOT2A_DriveMode_0_ADDR;
#pragma	ioport	MOT2A_DriveMode_1_ADDR:	0x105
BYTE			MOT2A_DriveMode_1_ADDR;
#pragma	ioport	MOT2A_DriveMode_2_ADDR:	0x7
BYTE			MOT2A_DriveMode_2_ADDR;
#pragma	ioport	MOT2A_GlobalSelect_ADDR:	0x6
BYTE			MOT2A_GlobalSelect_ADDR;
#pragma	ioport	MOT2A_IntCtrl_0_ADDR:	0x106
BYTE			MOT2A_IntCtrl_0_ADDR;
#pragma	ioport	MOT2A_IntCtrl_1_ADDR:	0x107
BYTE			MOT2A_IntCtrl_1_ADDR;
#pragma	ioport	MOT2A_IntEn_ADDR:	0x5
BYTE			MOT2A_IntEn_ADDR;
#define MOT2A_MASK 0x10
// MOT2B address and mask defines
#pragma	ioport	MOT2B_Data_ADDR:	0x4
BYTE			MOT2B_Data_ADDR;
#pragma	ioport	MOT2B_DriveMode_0_ADDR:	0x104
BYTE			MOT2B_DriveMode_0_ADDR;
#pragma	ioport	MOT2B_DriveMode_1_ADDR:	0x105
BYTE			MOT2B_DriveMode_1_ADDR;
#pragma	ioport	MOT2B_DriveMode_2_ADDR:	0x7
BYTE			MOT2B_DriveMode_2_ADDR;
#pragma	ioport	MOT2B_GlobalSelect_ADDR:	0x6
BYTE			MOT2B_GlobalSelect_ADDR;
#pragma	ioport	MOT2B_IntCtrl_0_ADDR:	0x106
BYTE			MOT2B_IntCtrl_0_ADDR;
#pragma	ioport	MOT2B_IntCtrl_1_ADDR:	0x107
BYTE			MOT2B_IntCtrl_1_ADDR;
#pragma	ioport	MOT2B_IntEn_ADDR:	0x5
BYTE			MOT2B_IntEn_ADDR;
#define MOT2B_MASK 0x20
// MOT3A address and mask defines
#pragma	ioport	MOT3A_Data_ADDR:	0x4
BYTE			MOT3A_Data_ADDR;
#pragma	ioport	MOT3A_DriveMode_0_ADDR:	0x104
BYTE			MOT3A_DriveMode_0_ADDR;
#pragma	ioport	MOT3A_DriveMode_1_ADDR:	0x105
BYTE			MOT3A_DriveMode_1_ADDR;
#pragma	ioport	MOT3A_DriveMode_2_ADDR:	0x7
BYTE			MOT3A_DriveMode_2_ADDR;
#pragma	ioport	MOT3A_GlobalSelect_ADDR:	0x6
BYTE			MOT3A_GlobalSelect_ADDR;
#pragma	ioport	MOT3A_IntCtrl_0_ADDR:	0x106
BYTE			MOT3A_IntCtrl_0_ADDR;
#pragma	ioport	MOT3A_IntCtrl_1_ADDR:	0x107
BYTE			MOT3A_IntCtrl_1_ADDR;
#pragma	ioport	MOT3A_IntEn_ADDR:	0x5
BYTE			MOT3A_IntEn_ADDR;
#define MOT3A_MASK 0x40
// MOT3B address and mask defines
#pragma	ioport	MOT3B_Data_ADDR:	0x4
BYTE			MOT3B_Data_ADDR;
#pragma	ioport	MOT3B_DriveMode_0_ADDR:	0x104
BYTE			MOT3B_DriveMode_0_ADDR;
#pragma	ioport	MOT3B_DriveMode_1_ADDR:	0x105
BYTE			MOT3B_DriveMode_1_ADDR;
#pragma	ioport	MOT3B_DriveMode_2_ADDR:	0x7
BYTE			MOT3B_DriveMode_2_ADDR;
#pragma	ioport	MOT3B_GlobalSelect_ADDR:	0x6
BYTE			MOT3B_GlobalSelect_ADDR;
#pragma	ioport	MOT3B_IntCtrl_0_ADDR:	0x106
BYTE			MOT3B_IntCtrl_0_ADDR;
#pragma	ioport	MOT3B_IntCtrl_1_ADDR:	0x107
BYTE			MOT3B_IntCtrl_1_ADDR;
#pragma	ioport	MOT3B_IntEn_ADDR:	0x5
BYTE			MOT3B_IntEn_ADDR;
#define MOT3B_MASK 0x80
// MOT0EN address and mask defines
#pragma	ioport	MOT0EN_Data_ADDR:	0x8
BYTE			MOT0EN_Data_ADDR;
#pragma	ioport	MOT0EN_DriveMode_0_ADDR:	0x108
BYTE			MOT0EN_DriveMode_0_ADDR;
#pragma	ioport	MOT0EN_DriveMode_1_ADDR:	0x109
BYTE			MOT0EN_DriveMode_1_ADDR;
#pragma	ioport	MOT0EN_DriveMode_2_ADDR:	0xb
BYTE			MOT0EN_DriveMode_2_ADDR;
#pragma	ioport	MOT0EN_GlobalSelect_ADDR:	0xa
BYTE			MOT0EN_GlobalSelect_ADDR;
#pragma	ioport	MOT0EN_IntCtrl_0_ADDR:	0x10a
BYTE			MOT0EN_IntCtrl_0_ADDR;
#pragma	ioport	MOT0EN_IntCtrl_1_ADDR:	0x10b
BYTE			MOT0EN_IntCtrl_1_ADDR;
#pragma	ioport	MOT0EN_IntEn_ADDR:	0x9
BYTE			MOT0EN_IntEn_ADDR;
#define MOT0EN_MASK 0x10
// MOT1EN address and mask defines
#pragma	ioport	MOT1EN_Data_ADDR:	0x8
BYTE			MOT1EN_Data_ADDR;
#pragma	ioport	MOT1EN_DriveMode_0_ADDR:	0x108
BYTE			MOT1EN_DriveMode_0_ADDR;
#pragma	ioport	MOT1EN_DriveMode_1_ADDR:	0x109
BYTE			MOT1EN_DriveMode_1_ADDR;
#pragma	ioport	MOT1EN_DriveMode_2_ADDR:	0xb
BYTE			MOT1EN_DriveMode_2_ADDR;
#pragma	ioport	MOT1EN_GlobalSelect_ADDR:	0xa
BYTE			MOT1EN_GlobalSelect_ADDR;
#pragma	ioport	MOT1EN_IntCtrl_0_ADDR:	0x10a
BYTE			MOT1EN_IntCtrl_0_ADDR;
#pragma	ioport	MOT1EN_IntCtrl_1_ADDR:	0x10b
BYTE			MOT1EN_IntCtrl_1_ADDR;
#pragma	ioport	MOT1EN_IntEn_ADDR:	0x9
BYTE			MOT1EN_IntEn_ADDR;
#define MOT1EN_MASK 0x20
// MOT2EN address and mask defines
#pragma	ioport	MOT2EN_Data_ADDR:	0x8
BYTE			MOT2EN_Data_ADDR;
#pragma	ioport	MOT2EN_DriveMode_0_ADDR:	0x108
BYTE			MOT2EN_DriveMode_0_ADDR;
#pragma	ioport	MOT2EN_DriveMode_1_ADDR:	0x109
BYTE			MOT2EN_DriveMode_1_ADDR;
#pragma	ioport	MOT2EN_DriveMode_2_ADDR:	0xb
BYTE			MOT2EN_DriveMode_2_ADDR;
#pragma	ioport	MOT2EN_GlobalSelect_ADDR:	0xa
BYTE			MOT2EN_GlobalSelect_ADDR;
#pragma	ioport	MOT2EN_IntCtrl_0_ADDR:	0x10a
BYTE			MOT2EN_IntCtrl_0_ADDR;
#pragma	ioport	MOT2EN_IntCtrl_1_ADDR:	0x10b
BYTE			MOT2EN_IntCtrl_1_ADDR;
#pragma	ioport	MOT2EN_IntEn_ADDR:	0x9
BYTE			MOT2EN_IntEn_ADDR;
#define MOT2EN_MASK 0x40
// MOT3EN address and mask defines
#pragma	ioport	MOT3EN_Data_ADDR:	0x8
BYTE			MOT3EN_Data_ADDR;
#pragma	ioport	MOT3EN_DriveMode_0_ADDR:	0x108
BYTE			MOT3EN_DriveMode_0_ADDR;
#pragma	ioport	MOT3EN_DriveMode_1_ADDR:	0x109
BYTE			MOT3EN_DriveMode_1_ADDR;
#pragma	ioport	MOT3EN_DriveMode_2_ADDR:	0xb
BYTE			MOT3EN_DriveMode_2_ADDR;
#pragma	ioport	MOT3EN_GlobalSelect_ADDR:	0xa
BYTE			MOT3EN_GlobalSelect_ADDR;
#pragma	ioport	MOT3EN_IntCtrl_0_ADDR:	0x10a
BYTE			MOT3EN_IntCtrl_0_ADDR;
#pragma	ioport	MOT3EN_IntCtrl_1_ADDR:	0x10b
BYTE			MOT3EN_IntCtrl_1_ADDR;
#pragma	ioport	MOT3EN_IntEn_ADDR:	0x9
BYTE			MOT3EN_IntEn_ADDR;
#define MOT3EN_MASK 0x80
