//*****************************************************************************
//*****************************************************************************
//  FILENAME: I2CHW_1.h
//   Version: 1.4, Updated on 2004/12/22 at 15:01:22
//  Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
//
//  DESCRIPTION: I2Cs User Module C Language interface file
//               for the (25/26xxx 22/24/26/27/28xxx) PSoC family of devices
//-----------------------------------------------------------------------------
//  Copyright (c) Cypress MicroSystems 2000-2004. All Rights Reserved.
//*****************************************************************************
//*****************************************************************************

#include <m8c.h>

/* Create pragmas to support proper argument and return value passing */
#pragma fastcall16  I2CHW_1_Start
#pragma fastcall16  I2CHW_1_DisableInt
#pragma fastcall16  I2CHW_1_EnableInt
#pragma fastcall16  I2CHW_1_Stop
#pragma fastcall16  I2CHW_1_EnableSlave
#pragma fastcall16  I2CHW_1_DisableSlave
#pragma fastcall16  I2CHW_1_EnableMstr
#pragma fastcall16  I2CHW_1_DisableMstr
#pragma fastcall16  I2CHW_1_InitWrite
#pragma fastcall16  I2CHW_1_InitRamRead
#pragma fastcall16  I2CHW_1_InitFlashRead
#pragma fastcall16  I2CHW_1_bReadI2CStatus
#pragma fastcall16  I2CHW_1_ClrRdStatus
#pragma fastcall16  I2CHW_1_ClrWrStatus

//-------------------------------------------------
// pragma register definitions.
//-------------------------------------------------
#pragma ioport  I2CHW_1_CFG: 0x0D6  // I2C Configuration Register
BYTE               I2CHW_1_CFG;

#define  I2C_BUSERRIE    0x20
#define  I2C_STOPIE      0x10
#define  I2C_CLKR1       0x08
#define  I2C_CLKR0       0x04
#define  I2C_M_EN        0x02
#define  I2C_S_EN        0x01


#pragma ioport  I2CHW_1_SCR: 0x0D7  // I2C Status and Control Register
BYTE               I2CHW_1_SCR;

#define  I2CM_BUSERR     0x80
#define  I2CM_LOSTARB    0x40
#define  I2C_STOP_ST     0x20
#define  I2C_ACKOUT      0x10
#define  I2C_ADDRIN      0x08
#define  I2C_TX          0x04 ;compliment is RX
#define  I2C_LST_BIT     0x02
#define  I2C_BYTE_COMPL  0x01


#pragma ioport  I2CHW_1_DR: 0x0D8  // I2C Status and Control Register
BYTE               I2CHW_1_DR;

#pragma ioport  I2CHW_1_MSCR: 0x0D9  // I2C Status and Control Register
BYTE               I2CHW_1_MSCR;

#define  I2CM_BUSBUSY    0x08
#define  I2CM_MASTEROP   0x04
#define  I2CM_RESTRT     0x02
#define  I2CM_SNDSTRT    0x01


//-------------------------------------------------
// Prototypes of the I2CHW_1 API.
//-------------------------------------------------
extern void  I2CHW_1_Start(void);			                                 //proxy class 1
extern void  I2CHW_1_DisableInt(void);		                             //proxy class 1
extern void  I2CHW_1_EnableInt(void);		                              //proxy class 1
extern void  I2CHW_1_Stop(void);			                                  //proxy class 1
extern void  I2CHW_1_EnableSlave(void);	                             //proxy class 1
extern void  I2CHW_1_DisableSlave(void);	                            //proxy class 1
extern void  I2CHW_1_EnableMstr(void);		                             //proxy class 1
extern void  I2CHW_1_DisableMstr(void);	                             //proxy class 1
extern void  I2CHW_1_InitWrite(BYTE * pI2CHW_1_WriteBuf, BYTE  I2CHW_1_Write_Count);	 //proxy class 1
extern void  I2CHW_1_InitRamRead(BYTE * pI2CHW_1_ReadBuf, BYTE  I2CHW_1_Read_Count);	 //proxy class 1
extern void  I2CHW_1_InitFlashRead(const BYTE * pI2CHW_1_flashaddr,  unsigned int I2CHW_1_Read_CountHI);	   //proxy class 1
extern BYTE  I2CHW_1_bReadI2CStatus(void);	                          //proxy class 1
extern void  I2CHW_1_ClrRdStatus(void);	                             //proxy class 1
extern void  I2CHW_1_ClrWrStatus(void);	                             //proxy class 1


#define I2CHW_1_READ_BUFTYPE                 0x1

//I2CHW_1_SlaveStatus byte, Status Bit definitions
#define  I2CHW_RD_NOERR                      0x1      //read completed without errors
#define  I2CHW_RD_OVERFLOW                   0x2      //master read more bytes than were contained in read buffer
#define  I2CHW_RD_COMPLETE                   0x4      //last read transaction is complete
#define  I2CHW_READFLASH                     0x8      //set- next read will use flash read buffer, clear- next read will use ram read buffer
#define  I2CHW_WR_NOERR                      0x10     //write completed without errors
#define  I2CHW_WR_OVERFLOW                   0x20     //received bytes exceeded write buffer length
#define  I2CHW_WR_COMPLETE                   0x40     //indicates eithe a stop or new addr was rec'd after a write to slave.
#define  I2CHW_ISR_NEW_ADDR                  0x40     //New address received (can infer that previous transaction is complete)
#define  I2CHW_ISR_ACTIVE                    0x80     //ISR for I2C is active

// end of file I2CHW_1.h
